The present invention is generally directed to system-on-a-chip (SoC) devices and, in particular, to a SoC device that includes an embedded field programmable gate array (FPGA) circuit that performs built-in self test (BIST) functions.
The speed, power, and complexity of integrated circuits, such as microprocessor chips, random access memory (RAM) chips, application specific integrated circuit (ASIC) chips, and the like, have increased dramatically in the last twenty years. More recently, these increases have led to development of so-called system-on-a-chip (SoC) devices. A SoC device allows nearly all of the components of a complex system, such as a cell phone or a television receiver, to be integrated onto a single piece of silicon. This level of integration greatly reduces the size and power consumption of the system, while generally also reducing manufacturing costs.
The complexity of state-of-the-art integrated circuits, particularly SoC devices, has increased the likelihood of a manufacturing defect occurring on the chip. To increase the reliability of integrated circuits and to detect error conditions and defective chips more rapidly, it is common practice to incorporate built-in self test (BIST) circuitry in SoC devices and other type of integrated circuits. BIST circuits are commonly used for memories, such as static random access memories (SRAM), dynamic random access memories (DRAM), flash RAM, and the like. State-of-the-art chip level BIST circuitry uses a dedicated hardware controller to execute the BIST testing and to report the pass or fail result to an external device. The BIST tests may be automatically generated for a given block of logic.
However, adding built-in self test circuitry to a system-on-a-chip device or other integrated circuit presents additional problems. Hardware-based BIST circuits occupy valuable space on the integrated circuit die. As the level of sophistication of self-testing increases, so does the size and complexity of the BIST circuitry. This results in a tradeoff between silicon area and detection sensitivity. Furthermore, the BIST circuitry itself may cause errors. This is particularly true as the complexity of the BIST circuit increases. Still another problem with BIST circuitry is that hardware BIST devices have a fixed test functionality that is determined at tapeout.
Therefore, there is a need in the art for system-on-a-chip (SoC) devices and other large scale integrated circuits that implement improved BIST functionality. In particular, there is a need for BIST circuitry that occupies a minimum amount of space on an integrated circuit chip. More particularly, there is a need for hardware-based BIST devices that are flexible enough to allow modification of BIST testing after the BIST circuit has been fabricated on an integrated circuit.
The present invention discloses a system-on-a-chip (SoC) device in which a pre-existing embedded file programmable gate array (FPGA) circuit in the SoC device performs the BIST function for the remainder of the SoC device. The embedded FPGA circuit normally performs some other function in the SoC device. However, upon boot-up or the occurrence of some other event, the embedded FPGA is configured to perform BIST testing. If the SoC device passes the BIST testing, the embedded FPGA is re-configured to perform the system function that the embedded FPGA normally performs.
The operation of an embedded FPGA according to the principles of the present invention may be as follows:
1) At power-up a specific BIST device or FPGA BIST code for the FPGA checks the FPGA integrity;
2) If the FPGA passes its own self-test, a bitstream configuration (i.e., program instructions) representing the SoC BIST code for the remainder of the SoC chip is loaded into the FPGA;
3) The SoC BIST code sets up the FPGA hardware to perform an exhaustive hardware test of the system; and
4) Once the SoC BIST function is completed, the embedded FPGA can be reprogrammed to be used as a block of embedded reconfigurable FPGA logic.
Because the FPGA is reconfigurable, the BIST procedures can evolve as certain failure modes or marginal operations are identified by repeated testing. Also, if certain tests prove to be redundant, then the BIST testing can be modified so that the run-time of the tests can be optimized. Using the FPGA for BIST testing and for the normal function of the FPGA allows more efficient usage of the silicon area by trading a small amount of time and area for efficiency and reusability.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a field programmable gate array for use in an integrated processing system and capable of testing other embedded circuit components in the integrated processing system. According to an advantageous embodiment of the present invention, the field programmable gate array is capable of detecting a trigger signal (such as a power reset) in the integrated processing system. In response to the trigger signal, the field programmable gate array receives first test program instructions from a first external source and executes the first test program instructions in order to test the other embedded circuit components in the integrated processing system.
According to one embodiment of the present invention, the field programmable gate array comprises a memory capable of storing the first test program instructions.
According to another embodiment of the present invention, the field programmable gate array is capable of controlling a configurable data bus coupling the field programmable gate array to the other embedded circuit components in the integrated processing system.
According to still another embodiment of the present invention, the field programmable gate array retrieves the first test program instructions from a second memory via the configurable data bus.
According to yet another embodiment of the present invention, the second memory is one of the other embedded circuit components in the integrated processing system.
According to a further embodiment of the present invention, the second memory is external to the integrated processing system.
According to a still further embodiment of the present invention, the field programmable gate array is capable of determining if the other embedded circuit components passed tests performed by the first test program instructions and wherein the field programmable gate array, in response to a determination that the other embedded circuit components passed the tests, is capable of receiving application program instructions from a second external source and executing the application program instructions.
According to a yet further embodiment of the present invention, the field programmable gate array stores the first test program instructions in an internal memory and overwrites the first test program instructions with the application program instructions.
In one embodiment of the present invention, the field programmable gate array is capable of receiving self test program instructions from a third external source and executing the self test program instructions in order to test the operation of the field programmable gate array.
In another embodiment of the present invention, the field programmable gate array is coupled to a built-in self test (BIST) circuit capable of testing the operation of the field programmable gate array.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.